1. Technical Field
The present invention relates to a single-phase power conversion device and a three-phase power conversion device. More specifically, the present invention relates to a single-phase power conversion device and a three-phase power conversion device for converting DC power to AC power in which a DC component in the AC power is suppressed by extracting the DC component from the output terminal voltage and correcting a target current.
2. Related Art
Many power conversion devices have a transformer to insulate a converter thereof from a load or to make the converter output compatible with the system voltage of the load. When a DC component is introduced into the input voltage to the transformer on the load side because of temperature drift or offset in the control system, the iron core of the transformer is magnetized in one direction by the DC component, which causes uneven distribution of magnetic flux called biased magnetization. Then, the problem arises that the excitation inductance of the transformer extremely decreases to cause flow of excessively large excitation current, distortion of output voltage, local temperature rise in the transformer, increase of electromagnetic noise and so on, and the AC power supplied from the power conversion device becomes unstable.
As a method for solving the problem, a DC component suppression method as follows has been disclosed: A saturable reactor and a reactor which allows excitation current proportional to the number of interlinking magnetic flux to flow through it are connected in parallel on the primary side of a transformer. A DC component is detected from the excitation current flowing through the reactors and fed back to the control of an inverter control circuit for a converter to compensate for the biased magnetization of the transformer. When no DC component is contained in the AC power outputted from the converter, a positive-negative symmetric current flows through the reactors and no DC component is generated in the output from an operational amplifier for integrating the current flowing through the reactors. When a DC component is contained in the AC power, a positive-negative asymmetric current flows through the reactors and a DC component proportional to the amount of magnetic saturation is detected in the output from the operational amplifier. Thus, the peak values of asymmetric positive and negative excitation currents flowing through the saturable reactor and the reactor are detected and the excitation currents in one cycle are integrated in an integration circuit to detect the DC component proportional to the amount of magnetic saturation in order to compensate for the biased magnetization of the transformer (see Patent Documents 1 and 2, for example).
On the other hand, an error tracking mode AC current control method has been proposed as a current control method for a power conversion device by the present inventors in which a target current is generated by a target current generation means and PWM (pulse width modulation) control of a converter is performed so that the output current can follow the target current (see Non-Patent Documents 1 and 2, for example).
FIG. 21 shows an example of the circuit configuration of a single-phase power conversion device employing an error tracking mode AC current control method. Designated as 1 is a DC power source (source voltage EB) for supplying DC power. A main circuit 100 is mainly composed of a converter 2 for converting the DC power supplied from the DC power source 1 to AC power, lines a1 and a2 through which a current flows to output terminals u1 and u2 via an inductor 3 (inductance component Lp), and a filter circuit 5 interposed between the inductor 3 and the output terminals u1 and u2 and connected between the output terminals u1 and u2 (between the lines a1 and a2). The filter circuit 5 is a circuit of a resistance RF and a capacitor CF connected in series and removes a switching frequency component in the AC power produced by the converter 2. The converter 2 has a full bridge circuit composed of power devices (semiconductor switch elements). As the semiconductor switch elements, IGBTs (insulated gate bipolar transistors), for example, can be used. Designated as 4 is a load connected to the output terminals u1 and u2.
Designated as 18 is a voltage detection means for detecting a filter voltage v(t) applied across the connection points of the filter circuit 5 and the lines a1 and a2 as an output terminal voltage. Designated as 19 is a first current detection means for detecting an output current ip(t) flowing from the converter 2 to the inductor 3. Designated as 7 is a second current detection means for detecting a load current is(t) flowing from the output terminals u1 and u2 to the load 4. The output current ip(t) is detected from the line a1 or a2 at a point in the vicinity of the converter 2, and the load current is(t) is detected from the line a1 or a2 at a point in the vicinity of the output terminal u1 or u2. The inductor 3 is used to control the output current ip(t). Designated as 17 is a PWM (pulse width modulation) control means (converter control means) for controlling the converter 2 and controls the converter 2 by supplying on-off signal pulses to the gates of a plurality of semiconductor switch elements of the converter 2. The control of the output current ip(t) is performed by gate control by the PWM control means 17. The symbol t represents time.
Designated as 110 is a target current generation means for generating a target current j(t) as a target value for the output current ip(t) by calculation. Designated as 13, 9 and 14 in the target current generation means 110 are first, second and third amplifiers with amplification factors of α, β and γ, respectively, for amplifying received input signals.
Designated as 10 is a filter voltage command means for generating a filter voltage command Vc(t) as a target value for the output terminal voltage, that is, the filter voltage v(t), as 11 is a filter current command means for generating a filter current command iCF(=CF(dvc/dt) as a target value for the fitter current flowing through the capacitor CF of a filter, and as 12 is a PWM current deviation compensation means for generating a deviation compensation command D(t) for compensating for the deviation between the output current ip(t) and the target current j(t).
FIG. 22A and FIG. 22B shows an example of the process flow of the control of the power conversion in the above single-phase power conversion device. As a step of converting DC power to AC power to be supplied to the load, DC power is converted to single-phase AC power in the converter 2 (step S1), and the AC power is supplied to the load 4 (step S2).
The output terminal voltage applied to the load 4, that is, the filter voltage v(t) applied across the connection points of the filter circuit 5 and the lines a1 and a2 is detected by the voltage detection means 18 (step S3), the load current is(t) flowing to the load 4 is detected by the second current detection means 7 (step S4), and the output current ip(t) flowing from the converter 2 to the inductor 3 (inductance component Lp) is detected by the first current detection means 19 (step S5).
The process of control of the target current generation means 110 is next described.
The filter voltage command Vc(t) generated by the filter voltage command means 10 (step S6) and the filter voltage v(t) detected by the voltage detection means 18 are subjected to subtraction in a second adder 15 to obtain the error therebetween (step S7). The error is multiplied by α in the first amplifier 13 (step S8), and the result is inputted into a fourth adder 16.
The load current is(t) detected by the second current detection means 7 is multiplied by β in the second amplifier 9 (step S9), and the result is inputted into the fourth adder 16 and serves as feedforward for the load current is(t).
The filter current command iCF generated by the filter current command means 11 (step S10) is multiplied by γ in the third amplifier 14 (step S11), and the result is inputted into a third adder 21.
The deviation compensation command D(t) generated by the PWM current deviation compensation means 12 (step S12), which is used to compensate for the deviation between the target current j(t) and an actual output current ip(t) flowing from the converter 2 to the inductor 3, is inputted into the third adder 21 and added to the filter current command iCF multiplied by γ (step S13).
The filter voltage error (filter voltage command Vc(t)−filter voltage v(t)) multiplied by α, the load current is(t) multiplied by β, and the result of addition in the third adder 21 are added in the fourth adder 16 to obtain a target current j(t) as an output therefrom (step S14′). The output voltage ip(t) detected by the first current detection means 19 is subtracted from the target current j(t) to obtain an error Δ(t) in a first adder 20 (step S15). The PWM control means 17 generates on-off signal pulses based on the error Δ(t) obtained in the first adder 20 and supplies the on-off signal pulses to the gates of the semiconductor switch elements of the converter 2 to control the converter 2 (step S16).
The case of a three-phase power conversion device is next described. The voltage detection means 18 detects line voltages (voltages between lines) vab(t), vbc(t) and vca(t) across three output terminals u, v and w the output terminal voltage <v(t)>. In the case of a three-phase power conversion device, the output current <ip(t)> detected by the first current detection means 19 has three components ipa(t), ipb(t) and ipc(t), and the load current <is(t)> detected by the second current detection means 7 has three components isa(t), isb(t) and isc(t). Accordingly, the target current <j(t)> also has three components ja(t), jb(t) and jc(t) corresponding to three phases, and the target current generation means 110 processes the three components. Here, the symbol <> represents a vector quantity (the same is hereinafter applied)
FIG. 23 shows an example of the circuit configuration of a three-phase power conversion device employing an error tracking mode AC current control method. Those parts having the same functions as those in FIG. 21 are designated in the drawing by the same reference numerals, and their description is omitted. The differences from the device shown FIG. 21 are mainly described. The converter 2 outputs three-phase AC power as the AC power. The main circuit 100 is composed of the converter 2, three lines a, b and c through which a current flows from the converter 2 to output terminals u, v and w via inductors 3 (inductance components LPa, LPb and LPc) and a filter circuit 5 interposed between the inductors 3 and the output terminals u, v and w and connected between the output terminals u, v and w (lines a, b and c). The filter circuit 5 has a circuit of three capacitors CF connected in a delta configuration and resistances RF interposed between the three terminals of the delta configuration and the three lines a, b and c, and functions as a filter for removing switching frequency components between the three phases as in the case with a single-phase power conversion device.
A voltage detection means 18 is located in the vicinity of the filter circuit 5 and detects a filter voltage <v(t)> (vab(t), vbc(t), vca(t)) applied across the connection points of the filter circuit 5 and the lines a, b and c (that is, across lines a and b, lines b and c and lines c and a) as the output terminal voltage v(t). A first current detection means 19 is located in the vicinity of the converter 2 on the three lines a, b and c and detects an output current <ip(t)> (ipa(t), ipb(t), ipc(t)) flowing from the converter 2 to the three inductors 3 (inductance components Lpa, Lpb and Lpc). A second current detection means 7 is located in the vicinity of the output terminals u, v and w on the lines a, b and c and detects a load current <is(t)>(isa(t), isb(t), isc(t)) flowing through the lines a, b and c.
A signal conversion means 120 has a first dq transformer 24 for dq transformation of the filter voltage <v(t)>(vab(t), vbc(t), vca(t) detected by the voltage detection means 18, a low-pass filter 25 interposed between the first dq transformer 24 and the second adder 15 in the target current generation means 110 for removing a high-frequency component, a second dq transformer 26 for dq transformation of the load current <is(t)>(isa(t), isb(t), isc(t)) detected by the second current detection means 7, and an inverse dq transformer 27 for inverse dq transformation of an output value <jdq(t)> from the fourth adder 16 in the target current generation means 110 and outputting target current <j(t)>(ja(t), jb(t), jc(t)). In the case of a three-phase power conversion device, a first adder 20 calculates an error <Δ(t)>(Δa(t), Δb(t), Δc(t)) between the output currents <ip(t)>(ipa(t), ipb(t), ipc(t)) having three components and the target current <j(t)>(ja(t), jb(t), jc(t)) having three components and inputs it into the PWM control means 17.
In the target current generation means 110, the filter voltage command, the filter current command, and the deviation compensation command are generated by the filter voltage command means 10, the filter current command means 11, and the PWM current deviation compensation means 12, respectively, in the dq space, and the process up to inputting the output value <jdq(t)> into the inverse dq transformer 27 is performed in the dq space. As the flow of operation, the difference from FIG. 22A and FIG. 22B is that a step of inputting the output value <jdq(t)> into the inverse dq transformer 27 and outputting a target current <j(t)> (ja(t), jb(t), jc(t)) is added between the calculation in the forth adder 16 (step S14′) and the calculation in the first adder 20 (step S15). The processes are performed in the dq space for the convenience of operation.
The second current detection means 7, the first current detection means 19 and the voltage detection means 18 do not necessarily perform detection in all the three phases but have to perform detection in at least two phases. The brackets ( ) in FIG. 23 mean that the parts in the brackets can be omitted.
[Patent Document 1] JP-A-H05-316754 (Sections [0007] to [0014], FIGS. 1 to 6, etc.)
[Patent Document 2] JP-A-H06-217559 (Sections [0007] to [0013], FIGS. 1 to 7, etc.)
[Non-Patent Document 1] “Current Error Tracking Mode AC Current Waveform Control Method for Single-Phase Self Commutated Voltage Source Power Converters,” Masaaki Ohshima, IEEJ Transactions on Industry Applications Vol. 114 (1994) No. 3, pp. 289–298.
[Non-Patent Document 2] “A novel Three-Phase UPS Inverter Driven by Error-Tracking-Mode PWM Scheme,” Masaaki Ohshima, Fuminori Nakamura, Shinzo Tamai, Yuushin Yamamoto, Kouich Yoshida, IEEJ Transactions on Industry Applications Vol. 125 (2005) No. 2, pp. 164–173.